The ongoing miniaturization of integrated circuit feature sizes has a significant impact on the chip's size, performance, and power consumption. With every advance in technology, the circuit performance is improved due to shorter transistor channel lengths, lower threshold voltages, and reduced gate-oxide thicknesses. These dimension reductions however lead to increased power leakage due to increased sub-threshold leakage and gate oxide tunnelling currents. For 90 nm and smaller technologies (which refers to the minimum feature size, such as channel length) leakage power becomes as important as dynamic switching power in many applications.
To reduce time to market, modern large system chips (system on chips—SoCs) are designed using pre-designed and pre-verified logic blocks called cores. A power domain in the SoC can contain one or more of these cores. To minimize the power dissipation, large SoCs require efficient power management. For that purpose, it is very common in practise to equip every power domain in the SoC with power switches to enable power gating functionality. Based on the activity in the SoC and the data transactions from a power domain, power domains can be individually turned off through the power switch. In this way, the leakage power is minimized for the power domain which is turned-off, thus, leading to savings in the overall power consumption. A power management unit implements the control function to turn-off and to turn-on power domains in the SoC.
FIG. 1 shows an example power domain as part of a SoC with power gating functionality. The power switches of the cores are labelled SN for core number N. Each core is supplied from the main supply line 10. Its power supply is connected between the main power supply 10 and ground 12, with the power switch S between the main supply 10 and a respective supply node 14N of each core N. This power management scheme is suitable for digital, analogue or mixed-signal cores. A power management unit (PMU) 16 controls the power domain; it is shown schematically with a single output. There may be multiple PMUs and they may have multiple control outputs.
When a power domain is power-gated, the circuit discharges to a reference potential, so that the charge of the inactive power domain is not effectively utilized. A more energy-efficient approach is to reuse this charge for functional operation, which leads to an increased autonomy for portable applications or sensor networks.
When a core is powered ON using the scheme shown in FIG. 1, typically only half the power delivered by the power management unit (PMU) 16 is used to charge (or power up) the core. The rest of the power is spent in heating up the switches. A better way to charge the core is to charge it up in steps. This may or may not be possible depending on the amount of time available to power up the core.
Pakbaznia E., Charge Recycling in MTCMOS Circuits: Concept and Analysis, DAC2006 showed a charge-recycling approach for power domains. The approach is to reduce the energy when switching between active and sleep modes of power domains, e.g. charge recycling is done to reduce the switching power consumption during the active-to-sleep and sleep-to-active transitions of two independent power domains. This approach is of very limited use, because it only makes sense to apply it when different cores are set to sleep (power-down) and to active (power-on) mode at about the same time.